The present invention relates to an annealing method for an SOI substrate having a semiconductor layer such as a silicon layer formed on an insulator, in which the number of defects (HF defects) in an SOI layer (the semiconductor layer on the insulator) and, more specifically, the number of HF defects which increase as an SOI layer becomes thin is reduced by annealing the SOI substrate in a reducing gas atmosphere, and an SOI substrate using the annealing method.
Sato et al. has reported a technique of annealing an SOI (Semiconductor On Insulator) wafer in a reducing atmosphere, in which, e.g., annealing in hydrogen gas at 1,000xc2x0 C. yields so high planarity that the roughness on an SOI layer surface is 2 nm or less (Japanese Patent Laid-Open No. 05-217821 and U.S. Pat. No. 5,371,037).
This technique will be described with reference to FIGS. 6 and 7. An example using a vertical annealing furnace is shown in FIG. 6.
Referring to FIG. 6, reference numeral 101 denotes a furnace tube serving as a reactor. An atmospheric gas is supplied from a supply pipe 102 arranged at the upper portion and exhausted from an exhaust pipe 103 at the lower portion. Reference numeral 104 denotes a heater; and 105, a boat which is made of silicon carbide set on a heat barrier 107 arranged on a furnace lid 106 and holds a plurality of SOI substrates 108. The boat 105 is formed from silicon carbide manufactured by sintering. The boat 105 may have a coating of chemically synthesized silicon carbide that is synthesized by chemical vapor phase deposition on a surface of silicon carbide manufactured by sintering.
Annealing is performed in accordance with the following procedure. The furnace lid 106 is moved downward in advance. In this state, the SOI wafers 108 are set in the boat 105. The furnace lid 106 is moved to the position shown in FIG. 6 to place the SOI wafers 108 in the process chamber and close the opening portion of the furnace tube 101. The furnace lid 106 is operated by an elevating mechanism (not shown). The interior of the process chamber is replaced with a hydrogen gas atmosphere by supplying hydrogen gas from the supply pipe 102 into the furnace tube 101.
The flow of the atmospheric gas in the annealing furnace will be described with reference to FIG. 7. Referring to FIG. 7, reference numeral 101 denotes a furnace tube; 105, a boat made of silicon carbide; and 108, SOI substrates, as in FIG. 6. Reference numerals 114 and 115 denote atmospheric gas flows.
The speed of the atmospheric gas flow 115 near an SOI substrate surface during annealing can be substantially set to zero, i.e., the flow can be eliminated by equalizing intervals 116 and 117 between the boat 105 and the furnace tube 101.
The speed of the atmospheric gas flow 114 means the speed of a gas that passes through a region excluding the sectional area of the SOI substrate 108 from the sectional area of the furnace tube 101.
Next, the interior of the process chamber is heated to a predetermined processing temperature by the heater 104, and annealing is performed. After the elapse of a predetermined time, the temperature of the heater 104 is reduced, and then, nitrogen gas is supplied into the process chamber to replace the atmosphere. The furnace lid 106 is moved downward, and the SOI substrates 108 are unloaded. The processing temperature and time are determined in accordance with a desired annealing effect.
Another technique has been proposed in which an SOI substrate formed by bonding wafers manufactured by the CZ method (Czochralski method) is annealed in a reducing atmosphere using a rapid heating/cooling apparatus (rapid thermal annealer; to be referred to as an RTA apparatus hereinafter), thereby reducing COPs (crystal originated particles; defects observed in a silicon wafer formed by the CZ method) on an SOI layer surface (Japanese Patent Laid-Open No. 11-145020).
In addition, a technique has been proposed in which an SOI substrate formed by a method called a hydrogen ion implantation peeling method, in which a wafer with hydrogen ions implanted is bonded to another silicon wafer and then peeled to form an SOI substrate, and is annealed in a reducing atmosphere using an RTA apparatus, thereby removing the damaged layer or surface roughness of an SOI layer while maintaining the film thickness uniformity of the SOI layer (Japanese Patent Laid-Open Nos. 11-307472 and 12-124092).
One of the factors that decrease the yield of devices manufactured using SOI wafers is defects in a single-crystal Si layer (SOI layer).
Defects in an SOI layer include HF defects that are detected by dipping an SOI wafer in a concentrated HF solution (49%) at room temperature. HF defects considerably affect the electrical characteristic of a device.
HF defects are caused by various factors. Sanada et al. checked causes for HF defects in SOI wafers manufactured by a method called SIMOX (Separation by Implanted Oxygen) in which an SOI wafer is formed by implanting oxygen ions, and reported that a metal silicide forms on an SOI layer by metal contamination at the time of ion implantation or annealing and molten in HF dipping to cause HF defects (D. K. Sanada, J. Lasky, H. J. Hovel, K. Petrillo, and P. Roitian, Proc. of IEEE SOI Conf., (1994) p. 111.
Aga et al. reported that HF defects in an SOI substrate manufactured by bonding CZ wafers are caused by COPs (H. Aga, M. Nakano, K. Mitani, Jpn. J. Appl. Phys., (1999) p. 2694).
Aga et al. also described in this report that the density of these HF defects abruptly rises when the SOI layer thickness becomes 200 nm or less because small COPs at the SOI/BOX interface also cause HF defects as the SOI layer becomes thinner.
A manufacturing method (epitaxial layer transfer method) called ELTRAN (registered trademark) has been proposed in which a single-crystal layer is formed on a porous layer formed on a silicon substrate surface, and the single-crystal layer is transferred to another substrate (Japanese Patent No. 2608351).
In the SOI substrate manufactured by the above method, no COPs are formed on the SOI layer because the single-crystal silicon layer is formed by epitaxial growth by CVD (Chemical Vapor Deposition).
However, HF defects are sometimes observed even in an SOI wafer manufactured by the above method, as shown in FIG. 9.
Thinning an SOI layer is an important technical challenge in promoting the advantages of an SOI wafer, i.e., high-speed operation and low power consumption of a device.
For example, the ITRS (SIA, The International Technology Roadmap for Semiconductors (1999) p. 110) requires to reduce the thickness of an SOI layer to 30 to 200 nm until 2003 and further to 20 to 100 nm from 2004.
From this viewpoint, reducing the number of HF defects is a very important challenge not only in improving the yield of devices but also in promoting thinning an SOI layer.
Details of how the present inventors have reached the present invention will be described below.
The present inventors extensively studied HF defects in an SOI substrate having a silicon layer formed by epitaxial growth and found that the number of HF defects tends to abruptly increase when the thickness of an SOI layer becomes less than 100 nm and also that the HF defects become conspicuous when the SOI layer thickness becomes 70 nm or less as shown in FIG. 9. This tendency that the HF defect density abruptly rises as an SOI layer becomes thinner is consistent with the above-described report by Aga et al.
First, an SOI substrate manufacturing method using the epitaxial layer transfer method will be described below in detail with reference to FIG. 8.
As shown in FIG. 8, in step S31, a single-crystal silicon substrate 131 is prepared as the first substrate, and a porous layer 133 is formed at least on its major surface side. Porous silicon can be formed by anodizing the silicon substrate in an HF solution. The porous layer has a sponge structure in which pores with a diameter of 10xe2x88x921 to 10 nm are arranged at an interval of 10xe2x88x921 to 10 nm. Although the density of single-crystal silicon is 2.33 g/cmxe2x88x923, the density of pores can be changed within the range of 2.1 to 0.6 g/cmxe2x88x923 by changing the HF solution concentration between 20% to 50%, changing the alcohol adding ratio, or changing the current density. When the resistivity and electrical conductivity type of a portion as a prospective porous layer are modulated in advance, the porosity can be adjusted on the basis of the resistivity and electrical conductivity type. Under the same anodization conditions for p-type, the pore diameter in a Pxe2x88x92 silicon substrate becomes smaller than that in a P+ silicon substrate, though the pore density increases by one order of magnitude, i.e., the porosity is high. That is, the porosity can be controlled by changing the conditions, and the method is not limited. The porous layer 133 can have either a single-layer structure or a multi-layered structure in which a plurality of layers with different porosities are stacked. When ions are implanted such that the projection range is included in the porous layer formed by anodization, cavities are formed in pore walls in the porous layer near the projection range, so the porosity can be increased. Ion implantation can be executed either before or after porous layer formation by anodization. Ion implantation may be executed after a single-crystal semiconductor layer structure is formed on the porous layer 133.
In step S32, at least one non-porous single-crystal semiconductor layer 123 such as a single-crystal silicon layer is formed on the porous layer 133. The non-porous single-crystal semiconductor layer 123 is arbitrarily selected from a single-crystal silicon layer formed by epitaxial growth, a non-porous layer formed from the surface layer of the porous layer 133, and the like. When a silicon oxide layer 122 is formed on the non-porous single-crystal semiconductor layer 123 by thermal oxidation, an interface with a low interface level can be formed by the thermal oxidation between the buried oxide film and the non-porous single-crystal semiconductor layer such as a single-crystal silicon layer. In step S33, the major surface (bonding surface) of the semiconductor substrate on which the non-porous single-crystal silicon layer 123 is formed is brought into tight contact with the surface (bonding surface) of a second substrate 121 at room temperature. Before the substrates are brought into tight contact, they are preferably cleaned to remove deposits and foreign substances on the surface. The second substrate can be selected from a silicon substrate, a silicon substrate with a silicon oxide film formed thereon, a transparent substrate formed from silica or the like, and a sapphire substrate. However, any other substrate can be used as long as the surface to be bonded is sufficiently flat and smooth. FIG. 8 shows a state wherein the second substrate 121 and first substrate are bonded via the insulating layer 122. The silicon oxide layer 122 may be omitted.
In bonding, an insulating thin plate may be inserted between the first and second substrates to form a three-layered bonded structure.
Subsequently, an unnecessary portion on the lower surface side of the substrate 131 and the porous layer 133 are removed to expose the non-porous single-crystal silicon layer 123. To do this, the following two methods can be used, though any other method may be used.
As the first method, the first substrate 131 is removed from the lower surface side to expose the porous layer 133 (step S34).
Subsequently, the porous layer 133 is removed to expose the non-porous single-crystal silicon layer 123 (step S35).
The porous layer is preferably removed by selective etching. When a solution mixture containing at least hydrofluoric acid and hydrogen peroxide is used, porous silicon can be selectively etched with a selectivity ratio of 105 times with respect to non-porous single-crystal silicon. The etchant may contain a surfactant for preventing formation of bubbles on the structure surface. Especially, an alcohol such as ethyl alcohol is preferably used. If the porous layer is thin, the selective etching may be omitted.
As the second method, the substrates are separated in the porous layer 133 as a separation layer to obtain the state in step S34 shown in FIG. 8. To separate the substrates, a method of applying an external force such as a pressure, tensile force, shearing force, or a force of a wedge; a method of applying an ultrasonic wave; a method of heating the porous layer; a method of applying an internal pressure to the porous silicon by expanding the porous silicon from the periphery by oxidation; a method of applying thermal stress or softening the porous layer by heating the porous layer while pulse-controlling the temperature; or a method of injecting a fluid such as a water jet or gas jet can be used. However, any other method may be used.
In step S35, the porous layer 133 remaining on the upper surface side of the second substrate 121 is removed by etching. The porous etching method is the same as the method of exposing the porous layer 133 by etching. If the porous silicon layer 133 remaining on the second substrate 121 side has a very small and uniform thickness, wet etching of the porous layer using hydrofluoric acid and hydrogen peroxide need not be executed.
In step S36, the second substrate 121 is annealed in a reducing atmosphere containing hydrogen to remove an upper layer portion 125 having a three-dimensional pattern on the single-crystal silicon layer 123 by etching. At this time, reduction of boron concentration in the single-crystal silicon layer and surface planarization can also simultaneously be achieved.
In the semiconductor substrate obtained by the epitaxial layer transfer method, the single-crystal silicon layer 123 is formed on the entire region of the second substrate 121 as a flat and uniform thin layer having a large area. The thus obtained semiconductor substrate can be adequately used from the viewpoint of manufacturing an insulated electronic device.
If the surface roughness of the separated first single-crystal silicon substrate 131 still falls outside the allowable range even after the porous layer remaining on the separation surface is removed, surface planarization is executed. With this processing, the substrate can be used again as the first single-crystal silicon substrate 131 or the next second substrate 121.
The present inventors observed with a scanning electronic microscope HF defects in an SOI substrate after step S35 in FIG. 8, which is manufactured by the above method. FIG. 10 shows the scanning-electronic-microscopic image of an HF defect. The HF defect (marked by a circle in FIG. 10) has a small pinhole shape with a diameter of 60 nm or less. Since the shape is not tetrahedral but circular, it is not a COP. When the thickness of an SOI layer is less than 100 nm, the number of HF defects tends to abruptly increase, as shown in FIG. 9.
For an SOI substrate having a silicon layer formed by epitaxial growth, the present inventors also extensively studied HF defects which abruptly increase in number in an SOI substrate whose SOI layer (semiconductor layer on an insulator) has a thickness less then 100 nm or equal to or less than 70 nm.
Consequently, it was confirmed that the number of HF defects can be reduced by executing annealing described in Japanese Patent Laid-Open No. 05-217821.
This is probably because that in annealing in a hydrogen atmosphere, silicon atoms that are excited on the surface by the thermal energy move to reduce the surface energy, thereby filling the defects.
However, if the HF defects are so deep that the BOX layer is exposed, H2O produced by chemical reaction
SiO2+H2xe2x86x92SiO(↑)+H2Oxe2x80x83xe2x80x83(1) 
between SiO2 and H2 in a hot hydrogen atmosphere reacts with silicon as is given by
Si+H2Oxe2x86x92SiO(↑)+H2xe2x80x83xe2x80x83(2) 
As a result, the defects become more conspicuous.
Hence, when H2O produced by annealing a hydrogen atmosphere is removed from the SOI substrate surface, or production of H2O is suppressed, the defects can be prevented from becoming conspicuous, and the number of HF defects can be decreased.
The present invention has been made from the above viewpoint, and has as its object to propose a method of annealing an SOI substrate in a reducing atmosphere, which can suppress HF defects from becoming conspicuous upon silicon etching by H2O.
That is, according to the present invention, there is provided an SOI substrate annealing method of annealing an SOI substrate in a reducing atmosphere, characterized in that a thickness of an SOI layer of the SOI substrate is less than 100 nm, and the SOI substrate is annealed in a state wherein a flow of a reducing atmospheric gas parallel to a surface of the SOI substrate is generated near the surface of the SOI substrate by supplying the reducing atmospheric gas from a gas supply port provided near an edge portion of the SOI substrate,.
When the flow velocity of the atmospheric gas near the SOI substrate surface, which is parallel to the SOI substrate surface, is made to be larger than 0, the above-described H2O produced by the reaction between the SiO2 and H2 can be quickly removed from the substrate surface.
In addition, when the flow velocity of the atmospheric gas is made equal to or larger than the flow velocity of the atmospheric gas in the reactor, the effect of removing H2O as a reaction product can be increased.
The xe2x80x9caverage flow velocity of the atmospheric gas in the reactorxe2x80x9d means the average flow velocity of a gas flow from an atmospheric gas supply port to an exhaust port, which passes through a sectional area, that is perpendicular to the gas flow, of the reactor excluding the sectional area of the SOI substrate.
One of examples for calculating the average flow velocity of the atmospheric gas in the reactor is explained.
In this example, H2 gas flow rate is assumed 22 slm (standard liter/min; flow volume per 1 min at 1 atm and 0xc2x0 C.) and pressure in the reactor is assumed 80 Torr (0.1053 atm).
In the reactor of 2-3 cm height and 24-25 cm width, a sectional area of the reactor is estimated as 48-75 cm2.
Under the above conditions, H2 gas flow rate during the annealing process is estimated in accordance with Boyle""s law; 22/0.1053=209 (l/min).
Flow velocity is estimated; 209*1000/(48 to 75)=2.79 to 4.35 (m/min) (46 to 72.5 (cm/s)).
According to the present invention, there is also provided an SOI substrate annealing method characterized in that the flow of the atmospheric gas is a laminar flow on the substrate surface.
When the flow of the atmospheric gas is a laminar flow on the substrate surface, a uniform and stable HF defect reduction effect can be obtained on the entire surface of the SOI substrate.
In the present invention, a uniform and stable HF defect reduction effect can be obtained on the entire surface of the SOI substrate by rotating the SOI substrate during annealing.
According to the present invention, there is also provided an SOI substrate annealing method characterized in that wherein a temperature of a reactor member is lower than a substrate temperature in annealing.
In a high-temperature annealing furnace generally used in a semiconductor process, silica (SiO2) is used as the reactor member.
When high-temperature annealing is executed in a hydrogen gas atmosphere using the above annealing furnace, chemical reaction given by formula (1) occurs between the member and the atmospheric gas, and silicon etching takes place due to H2O produced by the reaction.
As in the present invention, when the temperature of the reactor member is lower than the substrate temperature in annealing, chemical reaction between the member and the atmospheric gas can be suppressed. For example, a Halogen lamp or induction heater is employed to suppress the chemical reaction between the reactor member and the atmospheric gas. Alternatively, the reactor may be air-cooled by blowing air to the reactor to suppress the chemical reaction between the member and the atmospheric gas. According to the present invention, there is also provided an SOI substrate annealing method characterized in that a pressure in a reactor in annealing is not more than an atmospheric pressure.
When the pressure in the annealing process is equal to or less than the atmospheric pressure, the mean free path of molecules in the reactor becomes long, and therefore, H2O can be quickly removed.
The reducing atmospheric gas in the processing step is preferably a gas mixture substantially containing hydrogen or hydrogen and an inert gas.
In an atmosphere containing hydrogen, even at a temperature equal to or lower than the melting point of silicon, at which the surface is not planarized in a nitrogen atmosphere or inert gas atmosphere, a defect filling effect can be obtained because silicon atoms that are sufficiently excited by the thermal energy move.
According to another aspect of the present invention, there is provided an SOI substrate annealing method characterized in that an SOI substrate whose SOI layer has a thickness of less than 100 nm is subjected to annealing, and the SOI substrate is annealed in a state wherein a flow of a reducing atmospheric gas parallel to a surface of the SOI substrate is generated near the surface of the SOI substrate by rotating the SOI substrate.
As described above, with annealing of the present invention, the number of HF defects which abruptly increase in an SOI substrate whose SOI layer has a silicon layer formed by epitaxial growth, contains no COP, and has a thickness smaller than 100 nm or a thickness of 70 nm or less can be reduced, and a high-quality SOI substrate can be manufactured.
According to the present invention, there is also provided an SOI substrate annealing method characterized in that a thickness of an SOI layer of the SOI substrate is less than 100 nm, and the SOI substrate is annealed in a state wherein a flow of a reducing atmospheric gas parallel to a surface of the SOI substrate is generated near the surface of the SOI substrate by rotating the SOI substrate.
Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof.